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rt9202 1 ds9202-09 march 2007www.richtek.com features l operate from 5v l 0.8v internal reference l drive two n-mosfets l voltage mode pwm control l fast transient response l fixed 300khz oscillator frequency l full 0 to 100% duty cycle l internal soft start l adaptive non-overlapping gate driver l over-current monitor uses mosfet r ds(on) l over-voltage protection uses low-side mosfet l rohs compliant and 100% lead (pb)-free pin configurations applications l motherboard power regulation for computers l subsystems power supplies l cable modems, set top box, and dsl modems l dsp and core communications processor supplies l memory power supplies l personal computer peripherals l industrial power supplies l 5v-input dc-dc regulators l low voltage distributed power supplies single synchronous buck pwm dc-dc controller ordering information general description the rt9202 is a single power supply pwm dc-dc converter controller designed to drive n-mosfet in a synchronous buck topology. the ic integrates the control, output adjustment, monitoring and protection functions in a small 8-pin package. the rt9202 uses a low gain voltage mode pwm control for simple application design. an internal 0.8v reference allows the output voltage to be precisely regulated to low voltage requirement. a fixed 300khz oscillator reduces the component size for saving board space. the rt9202 features over current protection, over voltage protection, and under voltage lock-out. the output current is monitored by sensing the voltage drop across the mosfet's r ds(on) , which eliminates the need for a current sensing resistor. (top view) sop-8 boot ugate gnd lgate vcc fb ocset phase 2 3 4 5 6 7 8 note : richtek pb-free and green products are : } rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. } suitable for use in snpb or pb-free soldering processes. } 100%matte tin (sn) plating. rt9202 package type s : sop-8 operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard)
rt9202 2 ds9202-09 march 2007 www.richtek.com typical application circuit figure 1. rt9202 powered from 5v only figure 2. rt9202 powered from 12v and 5v h : shutdown phase ocset fb vcc boot ugate gnd lgate rt9202 81 2 3 4 5 6 7 c2 1uf r2 250 c6 10nf + c3 1000uf l1 5uh ml mu r3 120 c4 1uf shnd q1 2n7002 r1 20k r4 10 5v + c5 1uf c1 470uf 12v v out 2.5v 5v phase ocset fb vcc boot ugate gnd lgate rt9202 81 2 3 4 5 6 7 c2 0.1uf r2 255 c6 10nf + c3 1000uf l2 5uh ml mu d1 ma732 r3 120 c4 1uf shnd h : shutdown q1 2n7002 r1 20k r410 5v + c5 1uf c1 470uf v out 2.5v
rt9202 3 ds9202-09 march 2007www.richtek.com function block diagram layout placement layout notes 1. put cin1 & cin2 to be near the mu drain and ml source nodes. 2. put rt9202 to be near the c out 3. put c boot as close as to boot pin 4. put c vcc as close as to vcc pin gnd vcc rt9202 boot c vcc 1uf c boot 0.1uf + c out 1000uf l 5uh mu d g s ml d g s + c in1 1uf c in2 470uf gnd return bias 0.8 reference power on reset soft start + - ovp + - uvp 1.1v + - error 0.8v 0.5v error amplifier + - pwm 300khz oscillator control logic + - oc 40ua vcc 6.0v regulation gnd fb vcc boot ocset ugate phase lgate
rt9202 4 ds9202-09 march 2007 www.richtek.com functional pin description boot (pin 1) this pin provides ground referenced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive a logic-level n-mosfet when operating at a single 5v power supply. this pin also could be powered from atx 12v, in this situation, an internal 6.0v regulator will supply to vcc pin for internal voltage bias. ugate (pin 2) connect ugate pin to the pwm converter's upper mosfet gate. this pin provides the gate drive for the upper mosfet. gnd (pin 3) signal and power ground for the ic. all voltage levels are measured with respect to this pin. lgate (pin 4) connect lgate to the pwm converter's lower mosfet gate. this pin provides the gate drive for the lower mosfet. vcc (pin 5) this is the main bias supply for the rt9202. this pin also provides the gate bias charge for the lower mosfet gate. the voltage at this pin is monitored for power-on reset (por) purpose. this pin is also the internal 6.0v regulator output powered from boot pin when boot pin is directly powered from atx 12v. fb (pin 6) this pin is connected to the pwm converter's output divider. this pin also connects to internal pwm error amplifier inverting input and protection monitor. ocset (pin 7) connect a resistor from this pin to the drain of the upper mosfet. this resistor, an internal 40 m a current source, and the upper mosfet on-resistance set the converter over-current trip point. an over-current trip cycles the soft- start function. the voltage at this pin is monitored for power-on reset (por) purpose and pulling this pin low with an open drain device will shut down the ic. phase (pin 8) this pin is used to monitor the voltage drop across the upper mosfet for over-current protection. ds(on) ocset ocset peak r r i i =
rt9202 5 ds9202-09 march 2007www.richtek.com electrical characteristics (v cc = 5v, t a = 25 c, unless otherwise specified.) parameter symbol test conditions min typ max units v cc supply current / regulated voltage nominal supply current i cc ugate, lgate open -- 3 6 ma regulated voltage from boot v cc v boot = 12v 5 6 7 v power-on reset rising v cc threshold v ocset = 4.5v 3.85 4.1 4.35 v v cc threshold hysteresis v ocset = 4.5v 0.3 0.5 0.7 v rising v ocset threshold 0.8 1.25 2.0 v reference reference voltage 0.784 0.8 0.816 v oscillator free running frequency 250 300 350 khz ramp amplitude d v osc -- 1.75 -- v p-p error amplifier dc gain 32 35 38 db pwm controller gate driver upper drive source r ugate boot= 12v boot-v ugate = 1v -- 7 11 w upper drive sink r ugate v ugate = 1v -- 5 7.5 w lower drive source r lgate v cc - v lgate = 1v, -- 4 6 w lower drive sink r lgate v lgate = 1v -- 2 4 w to be continued absolute maximum ratings (note 1) l supply input voltage, v cc -----------------------------------------------------------------------------------------7v l boot & ugate to gnd--------------------------------------------------------------------------------------------15v l input, output or i/o voltage ----------------------------------------------------------------------------------------gnd - 0.3v to 7v l power dissipation, p d @ t a = 25 c l sop-8-------------------------------------------------------------------------------------------------------------------0.625w l package thermal resistance (note 4) l sop-8, q ja --------------------------------------------------------------------------------------------------------------160 c/w l ambient temperature range---------------------------------------------------------------------------------------0 c to +70 c l lead temperature (soldering, 10 sec.)---------------------------------------------------------------------------260 c l storage temperature range---------------------------------------------------------------------------------------- - 65 c to +150 c l esd susceptibility (note 2) hbm (human body mode)------------------------------------------------------------------------------------------2kv mm (machine mode)-------------------------------------------------------------------------------------------------200v recommended operating conditions (note 3) l junction temperature range--------------------------------------------------------------------------------------- - 40 c to +125 c
rt9202 6 ds9202-09 march 2007 www.richtek.com parameter symbol test conditions min typ max units protection fb over-voltage trip fb rising 1.0 1.1 -- v fb under-voltage trip fb falling -- 0.5 0.6 v ocset current source i ocset v ocset = 4.5v 35 40 45 m a soft-start interval 1 2 4 ms note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. q ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard.
rt9202 7 ds9202-09 march 2007www.richtek.com typical operating characteristic dead time time (50ns/div) ugate lgate v cc = 5v dead time time (50ns/div) ugate lgate v cc = 5v time (50ms/div) v cc = 5v v out = 2.2v v cc v out power off power on time (2.5ms/div) v cc = 5v v out = 2.2v v cc v out load transient time (5us/div) v cc = 5v v out = 2.2v c out = 3000uf v out ugate load transient time (5us/div) v cc = 5v v out = 2.2v c out = 3000uf v out ugate
rt9202 8 ds9202-09 march 2007 www.richtek.com bootstrap wave form time (1us/div) v cc = 5v, v out = 2.2v ugate lgate phase short circuit hiccup time (5ms/div) v cc = 5v, v out = 2.2v ugate v out reference vs. temperature 0.796 0.797 0.798 0.799 0.800 0.801 0.802 0.803 -50050100150 temperature r e f e r e n c e ( v ) ( c) i ocset vs. temperature 20 25 30 35 40 45 50 55 -40-10205080110140 temperature i o c s e t ( u a ) ( c) por (rising/falling) vs. temperature 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 -50050100150 temperature p o r ( v ) ( c) falling rising oscillator frequency vs. temperature 270 275 280 285 290 295 300 305 310 315 -50050100150 temperature f r e q u e n c y ( k h z ) a ( c)
rt9202 9 ds9202-09 march 2007www.richtek.com application information the rt9202 operates at either single 5v power supply with a bootstrap ugate driver or 5v/12v dual-power supply form the atx smps. the dual- power supply is recommended for high current application, the rt9202 can deliver higher gate driving current while operating with atx smps based on dual-power supply. the bootstrap operation in a single power supply system, the ugate driver of rt9202 is powered by an external bootstrap circuit, as the figure 1. the boot capacitor, c boot , generates a floating reference at the phase pin. typically a 0.1 m f c boot is enough for most of mosfets used with the rt9202. the voltage drop between boot and phase is refreshed to a voltage of vcc - diode drop (v d ) while the low side mosfet turning on. dual power operation the rt9202 is designed to regulate a 6.0v at vcc pin automatically when boot pin is powered by 12v. in a system with atx 5v/12v power supply, the rt9202 is ideal for higher current application due to the higher gate driving capability, v ugate = 7v and v lgate = 6.0v. a rc (10 w /1 m f) filter is also recommended at boot pin to prevent the ringing induced from fast power on, as shown in figure 2. + 5v vcc lgate phase ugate boot r1 vcc c2 1uf rt9202 0.1uf d1 + 5v vcc lgate ugate boot r1 c2 1uf rt9202 1uf 6.0v regulation 10 c1 12v vcc 5v figure 1. single 5v power supply operation figure 2. dual power supply operation power on reset the power-on reset (por) monitors the supply voltage (normal +5v) at the vcc pin and the input voltage at the ocset pin. the vcc por level is 4.1v with 0.5v hysteresis and the normal level at ocset pin is 1.5v (see over-current protection). the por function initiates soft-start operation after all supply voltages exceed their por thresholds. soft start a built-in soft-start is used to prevent surge current from power supply input during power on. the soft-start voltage is controlled by an internal digital counter. it clamps the ramping of reference voltage at the input of error amplifier and the pulse-width of the output driver slowly. the typical soft-start duration is 2ms. over-current protection the over current protection (ocp) function of the rt9202 is triggered when the voltage across the r ds(on) of upper side mosfet that developed by drain current exceeds over-current tripping level. an external resistor (r ocset ) programs the over-current tripping level of the pwm converter. as shown on figure 3 the internal 40 m a current sink (i ocset ) develops a voltage across r ocset (v set ) that is referenced to v in . the drive signal enables the over-current comparator (oc). when the voltage across the upper mosfet (v ds(on) ) exceeds v set , the over- current comparator trips to set the over-current latch.
rt9202 10 ds9202-09 march 2007 www.richtek.com under voltage and over voltage protection the voltage at fb pin is monitored and protected against oc (over current), uv (under voltage), and ov (over voltage). the uv threshold is 0.5v and ov-threshold is 1.0v. both uv/ov detection have 30 m s triggered delay. when oc or uv trigged, a hiccup re-start sequence will be initialized, as shown in figure 4. only 3 times of trigger are allowed to latch off. hiccup is disabled during soft- start interval. shutdown pulling low the ocset pin can shutdown the rt9202 pwm controller as shown in typical application circuit. inductor selection the rt9202 was designed for v in = 5v, step-down application mainly. figure 5 shows the typical topology and waveforms of step-down converter. the ripple current of inductor can be calculated as follows: il ripple = (5v - v out )/l t on because operation frequency is fixed at 300khz, t on = 3.33 v out /5v the v out ripple is v out ripple = il ripple esr esr is output capacitor equivalent series resistor table 1 shows the ripple voltage of v out : vin = 5v gate control + - pwm oc drive vcc ocset r ocset v set+ v in = +5v v ds+ i d ugate phase i ocset 40uf over-current trip: v ds > v set dds(on)ocsetocset ir>ir v ocset = v in - v set v phase = v in - v ds 0a 0v 2v 4v i n t e r n a l s s i n d u c t o r c u r r e n t t1t2 t3 time count = 1 count = 2 count = 3 overload applied t0 both v set and v ds are referenced to v in and a small capacitor across r ocset helps v ocset tracking the variations of v in due to mosfet switching. the over- current function will be tripped at a peak inductor current (i peak ) determined by : the oc trip point varies with mosfet's r ds(on) temperature variations. the temperature coefficient of i ocset is 2500ppm that is used to compensate r ds(on) temperature variations. to avoid over-current tripping in the normal operating load range, determine the r ocset resistor value from the equation above with: 1.the maximum r sd(on) at the highest junction temperature 2.the minimum i ocset from the characteristics 3.determine i peak for i peak > i out(max) + ( d i)/2 where d i is the output inductor ripple current. figure 3 figure 4 ds(on) ocset ocset peak r r i i =
rt9202 11 ds9202-09 march 2007www.richtek.com v out 3.3v 2.5v 1.5v inductor 2 m h 5 m h 2 m h 5 m h 2 m h 5 m h 1000 m f (esr=53m w ) 100mv 40mv 110mv 44mv 93mv 37mv 1500 m f (esr=33m w ) 62mv 25mv 68mv 28mv 58mv 23mv 3000 m f (esr=21m w ) 40mv 16mv 43mv 18mv 37mv 15mv table 1 *refer to sanyo low esr series (ce, dx, px.....) the suggested l and c are as follows: 2 m h with 3 1500 m f c out 5 m h with 3 1000 m f c out figure 5 input / output capacitor high frequency/long life decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance to the pcb trace, as it could eliminate the performance from utilizing these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. the output capacitors are necessary for filtering output and stabilizing the close loop (see the pwm loop stability). for powering advanced, high-speed processors, it is required to meet with the requirement of fast load transient, high frequency capacitors with low esr/esl capacitors are recommended. another concern is high esr induced ripple may trigger uv or ov protections. pwm loop stability the rt9202 is a voltage mode buck controller designed for 5v step-down applications. the gain of error amplifier is fixed at 35db for simplified design. the output amplitude of ramp oscillator is 1.75v, the loop gain and loop pole/zero are calculated as follows : dc loop gain g a = lc filter pole p o = error amp pole p a = 300khz esr zero z o = the rt9202 bode plot as shown figure 6 is stable in most of application conditions. v i v o r c d l q c.c.m t on t off t s v l v i - v o - v o uq mi l i l = i o i l i q i q i d i d v l out v 0.8 1.75 5 35db lc 2 1 p esrc 2 1 p
rt9202 12 ds9202-09 march 2007 www.richtek.com figure 6 loop gain 40 30 20 10 1m 10k 1k 100 100k v out = 3.3v c out = 1500 m f(33m w ) l = 2 m h v out = 1.5v v out = 2.5v v out = 3.3v p o = 2.9khz z o = 3.2khz reference voltage because rt9202 use a low 35db gain error amplifier, shown in figure 7. the voltage regulation is dependent on v in & v out setting. the fb reference voltage of 0.8v were trimmed at v in = 5v & v out = 2.5v condition. in a fixed v in = 5v application, the fb reference voltage vs. v out voltage can be calculated as figure 8. figure 7 figure 8 f b ( v ) v out (v) 4 3.5 3 11.522.5 0.82 0.78 0.80 0.81 0.79 0.5 4.5 vin = 5v feedback divider the reference of rt9202 is 0.8v. the output voltage can be set using a resistor based divider as shown in figure 9. put the r1 and r2 as close as possible to fb pin and r2 should less than 1 k w to avoid noise coupling. the c1 capacitor is a speed-up capacitor for reducing output ripple to meet with the requirement of fast transient load. typically a 1nf to 0.1 m f is enough for c1. figure 9 v in + r1 c1 fb rt9202 v out l r2 <1k c out pwm layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. consider, as an example, the turn-off transition of the upper mosfet prior to turn-off, the upper mosfet was carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the low side mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selections, layout of the critical components, and use shorter and wider pcb traces help in minimizing the magnitude of voltage spikes. + - ea + - pwm 56k 1k + - fb rep 0.8v ramp 1.75v r1 r2
rt9202 13 ds9202-09 march 2007www.richtek.com there are two sets of critical components in a dc-dc converter using the rt9202. the switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power components and the pwm controller should be placed firstly. place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. place the output inductor and output capacitors between the mosfets and the load. also locate the pwm controller near by mosfets. a multi-layer printed circuit board is recommended. figure 10 shows the connections of the critical components in the converter. note that the capacitors cin and cout each of them represents numerous physical capacitors. use a dedicated grounding plane and use vias to ground all critical components to this layer. apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase node, but it is not necessary to oversize this particular island. since the phase node is subjected to very high dv/dt voltages, the stray capacitance formed between these island and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal routing. the pcb traces between the pwm controller and the gate of mosfet and also the traces connecting source of mosfets should be sized to carry 2a peak currents. figure 10 + + load + vccgnd rt9202 fb lgate ugate il iq1 v out q2 q1 iq2 5v gnd
rt9202 14 ds9202-09 march 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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